[fpc-devel] Error building xtensa rtl

[Christo Crause]

On Tue, Mar 31, 2020 at 7:39 AM Sven Barth via fpc-devel <
fpc-devel at lists.freepascal.org> wrote:

> Am 30.03.2020 um 22:07 schrieb Christo Crause via fpc-devel:
>
> I've noticed GCC uses the SLLI + SRAI instructions to perform sign
> extension on ESP8266.
>
> Since different CPUs can support different subsets of the Xtensa
> instructions do you think a finalizecode type function can be used as a
> post code generation step to map unsupported instructions to alternative
> sequences?
>
>
> These are simply different CPU types (-CpXXX or selected by the controller
> type) which the code generator will handle accordingly. Just like it's done
> with ARM, AVR and all other platforms.
>

Attach please find a patch to rtl/embedded/MakeFile* to handle subarch
similar to avr and others.
Also attached a patch that checks whether the SEXT instruction is available
for the current subarchitecture, else it generates SLLI + SRAI combination.

I post the patches here for review since I'm not sure this is necessarily
the style to be followed when checking capabilities.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freepascal.org/pipermail/fpc-devel/attachments/20200331/bb876d4d/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: makefile.patch
Type: text/x-patch
Size: 1571 bytes
Desc: not available
URL: <http://lists.freepascal.org/pipermail/fpc-devel/attachments/20200331/bb876d4d/attachment.bin>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: xtensa-sext-alternative.patch
Type: text/x-patch
Size: 3766 bytes
Desc: not available
URL: <http://lists.freepascal.org/pipermail/fpc-devel/attachments/20200331/bb876d4d/attachment-0001.bin>