<div dir="ltr">On Tue, Mar 31, 2020 at 7:39 AM Sven Barth via fpc-devel <<a href="mailto:fpc-devel@lists.freepascal.org">fpc-devel@lists.freepascal.org</a>> wrote:<br><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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<div>Am 30.03.2020 um 22:07 schrieb Christo
Crause via fpc-devel:<br></div><blockquote type="cite"><div dir="ltr"><div class="gmail_quote"><div>I've noticed GCC uses the SLLIĀ + SRAI instructions to
perform sign extension on ESP8266.</div>
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<div>Since different CPUs can support different subsets of the
Xtensa instructions do you think a finalizecode type
function can be used as a post code generation step to map
unsupported instructions to alternative sequences?<br>
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These are simply different CPU types (-CpXXX or selected by the
controller type) which the code generator will handle accordingly.
Just like it's done with ARM, AVR and all other platforms.<br>
</div></blockquote><div><br></div><div>Attach please find a patch to rtl/embedded/MakeFile* to handle subarch similar to avr and others.</div><div>Also attached a patch that checks whether the SEXT instruction is available for the current subarchitecture, else it generates SLLI + SRAI combination.<br></div><div><br></div><div>I post the patches here for review since I'm not sure this is necessarily the style to be followed when checking capabilities.<br></div></div></div>