[fpc-devel] Error building xtensa rtl

Sven Barth pascaldragon at googlemail.com
Tue Mar 31 07:39:38 CEST 2020

Am 30.03.2020 um 22:07 schrieb Christo Crause via fpc-devel:
> On Sun, Mar 29, 2020 at 11:00 PM Florian Klämpfl 
> <florian at freepascal.org <mailto:florian at freepascal.org>> wrote:
>     Am 29.03.20 um 22:46 schrieb Christo Crause via fpc-devel:
>     > It seems that a different instruction sequence should be used
>     for sign
>     > extension for the lx106 subarch.
>     Ok, I see. Let me first integrate everything done so far in trunk,
>     then
>     we can continue with the details :)
> I've noticed GCC uses the SLLI + SRAI instructions to perform sign 
> extension on ESP8266.
> Since different CPUs can support different subsets of the Xtensa 
> instructions do you think a finalizecode type function can be used as 
> a post code generation step to map unsupported instructions to 
> alternative sequences?

These are simply different CPU types (-CpXXX or selected by the 
controller type) which the code generator will handle accordingly. Just 
like it's done with ARM, AVR and all other platforms.

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