[fpc-devel] Code generator issue for Cortex-M0 chips in trunk

[Nico Erfurth]

On 08.08.14 10:28, Michael Ring wrote:
> There seems to be a bug in the codegenerator for armv6m thumb code.
> 
> tst r0,#-2147483648
> 
> is not valid armv6m assembler code, documentation says that tst only can
> use registers:
> 
> TST Rn, Rm

Please try the attached patch, it should solve the problem, I'll commit
it after testing.

Nico


-------------- next part --------------
>From 89f5b4f1adc828bdc0628baa35166c1c9254b42e Mon Sep 17 00:00:00 2001
From: Nico Erfurth <ne at erfurth.eu>
Date: Fri, 8 Aug 2014 14:22:33 +0200
Subject: [PATCH 1/1] 16bit Thumb is not able to use tst with an immediate
 value

r28315 introduced an arm optimization which requires
  tst rX, #imm
to work. This is not available on 16bit thumb, I've disabled that
optimization on thumb for now.
---
 compiler/arm/narmadd.pas | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/compiler/arm/narmadd.pas b/compiler/arm/narmadd.pas
index 40fb94e..426622c 100644
--- a/compiler/arm/narmadd.pas
+++ b/compiler/arm/narmadd.pas
@@ -416,7 +416,7 @@ interface
         if (right.nodetype=ordconstn) and
            (tordconstnode(right).value=0) and
            ((nodetype in [equaln,unequaln]) or
-            (is_signed(left.resultdef) and (nodetype = lt_zero_swapped[nf_swapped in Flags]))
+            (not(GenerateThumbCode) and is_signed(left.resultdef) and (nodetype = lt_zero_swapped[nf_swapped in Flags]))
            ) then
           begin
             location_reset(location,LOC_FLAGS,OS_NO);
-- 
1.8.5.5