[fpc-devel] Some Opcodes missing in internal assembler for mips32r2

Sergei Gorelkin sergei_gorelkin at mail.ru
Mon Jun 17 08:12:49 CEST 2013

16.06.2013 22:17, Michael Ring пишет:
> I have now browsed through the current mips documentation and have created a file that includes all
> opcodes, the version they are first in (starting with mips32) and a small comment what the mnemonic
> does.
> This file is attached to this mail.
The problem here is that MIPS32 is not the first, but fifth version of MIPS instruction sets, 
preceded by MIPS I, MIPS II, MIPS III and MIPS IV. Currently there is no separation between 
instructions sets in compiler sources, but they need to appear one day. MIPS32 documentation is not 
correct in this respect, as it says e.g. that ADD is first supported by MIPS32, while it is actually 
MIPS I instruction.

The most accurate source is probably the GNU Opcode library, which is part of binutils.

> Out of this file it is easy to create both compiler/mips/strinst.inc and compiler/mips/opcode.inc.
> Now I am looking for additional lines that I will need to add to this file, to find out what is
> necessary I have created a list of mnemonics that exist only in the original opcode.inc file (see
> later)
> there are a number of entries in the form xxx64xxx and xxx32, xxxg and dxxx, all those do not seem
> to be valid for mips32 & up, where do those come from and which of those do I need to add?
xxx64xxx and xxxg are likely subject for removal, I've no idea where they came from. dxxx and xxx32 
are MIPS III instructions, as well as sdr,sdl,lwu and alike. A lot of other stuff (la, li, neg, 
mulo, seq, etc.) are macros that are expanded into several instructions.

> There's one very strange entry in opcode.inc: 'b '
> there is also 'b', is it necessary to have 'b ' ?
The codegenerator and optimizer expect conditional and unconditional branches to have distinct 
opcodes, this strange construction provides that.


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