[fpc-devel] Some Opcodes missing in internal assembler for mips32r2

Sun Jun 16 20:17:55 CEST 2013

I have now browsed through the current mips documentation and have 
created a file that includes all opcodes, the version they are first in 
(starting with mips32) and a small comment what the mnemonic does.
This file is attached to this mail.

Out of this file it is easy to create both compiler/mips/strinst.inc and 
compiler/mips/opcode.inc.

Now I am looking for additional lines that I will need to add to this 
file, to find out what is necessary I have created a list of mnemonics 
that exist only in the original opcode.inc file (see later)

there are a number of entries in the form xxx64xxx and xxx32, xxxg and 
dxxx, all those do not seem to be valid for mips32 & up, where do those 
come from and which of those do I need to add?

There's one very strange entry in opcode.inc: 'b '

there is also 'b', is it necessary to have 'b ' ?

Thank you,

Michael

'add64sub',
'b ',
'dadd',
'daddi',
'daddiu',
'daddu',
'ddiv',
'ddivg',
'ddivu',
'ddivug',
'div64sub',
'divg',
'divug',
'dli',
'dmfc1',
'dmodg',
'dmodug',
'dmtc1',
'dmul',
'dmulo',
'dmulou',
'dmult',
'dmultg',
'dmultu',
'dmultug',
'dneg',
'dnegu',
'drem',
'dremu',
'dsll',
'dsll32',
'dsllv',
'dsra',
'dsra32',
'dsrav',
'dsrl',
'dsrl32',
'dsrlv',
'dsub',
'dsubu',
'end_def'
'la',
'ld',
'ldl',
'ldr',
'li',
'lld',
'lwu',
'modg',
'modug',
'move',
'mul64sub',
'mulo',
'mulou',
'multg',
'multug',
'neg',
'neg64sub',
'negu',
'not',
'not64sub',
'or64sub',
'rem',
'remu',
'sar64sub',
'scd',
'sd',
'sdl',
'sdr',
'seq',
'sge',
'sgeu',
'sgt',
'sgtu',
'shl64sub',
'shr64sub',
'sle',
'sleu',
'sne',
'sub64sub',
'xor64sub',

Am 05.06.13 20:23, schrieb Michael Ring:
> Thank you, the startup code is compiling now, I will send you a patch 
> with the missing opcodes to have full support of mips32r2 soon.
>
> Michael
>
> Am 03.06.13 22:04, schrieb Sergei Gorelkin:
>> 29.05.2013 21:44, Michael Ring пишет:
>>> This is looking good now on first view, all statements seem to pass 
>>> through now.
>>>
>>> The only thing not working is the register error in mfc0 (and 
>>> friends) command.
>>>
>>> Now I will wade through some more code to find out why my nice param 
>>> -CpMIPS32R2 is ignored by
>>> assembler, it still defaults to MIPS2:
>>>
>> I hopefully fixed this issue in r24643, and the register naming issue 
>> in r24799.
>> Should you encounter more issues, do not hesitate to report them.
>>
>> Regards,
>> Sergei
>> _______________________________________________
>> fpc-devel maillist  -  fpc-devel at lists.freepascal.org
>> http://lists.freepascal.org/mailman/listinfo/fpc-devel
>>
>
> _______________________________________________
> fpc-devel maillist  -  fpc-devel at lists.freepascal.org
> http://lists.freepascal.org/mailman/listinfo/fpc-devel
>

-------------- next part --------------
// Translate this file with the following commands:
// cat opcodestrinst.txt | grep -v "^//" | grep -v "^$" | awk -F\| '{ print "A_" $1 ", // " $3 }' | sed -e "s,\.,_,g" >opcode.inc
// cat opcodestrinst.txt | grep -v "^//" | grep -v "^$" | sed -e "s,^P_,.,g"  -e "s,.SET,p_set,g" | awk -F\| '{ print "^" $1 "^, // " $3 }' | tr '[:upper:]' '[:lower:]' | sed "s,\^,\',g" >strinst.inc

//Assembler specific Commands
NONE|PRE|none
P_SET_NOMIPS16|PRE|nomips16
P_SET_NOREORDER|PRE|noreorder
P_SET_NOMACRO|PRE|nomacro
P_SET_MACRO|PRE|macro
P_SET_REORDER|PRE|set_reorder
P_SET_NOAT|PRE|set_noat
P_SET_AT|PRE|set_at
P_FRAME|PRE|frame
P_MASK|PRE|mask
P_FMASK|PRE|fmask
P_CPLOAD|PRE|cpload
P_CPRESTORE|PRE|cprestore
P_CPADD|PRE|cpadd

//CPU Arithmetic Instructions
ADD|MIPS32|Add Word
ADDI|MIPS32|Add Immediate Word
ADDIU|MIPS32|Add Immediate Unsigned Word
ADDU|MIPS32|Add Unsigned Word
CLO|MIPS32|Count Leading Ones in Word
CLZ|MIPS32|Count Leading Zeros in Word
DIV|MIPS32|Divide Word
DIVU|MIPS32|Divide Unsigned Word
MADD|MIPS32|Multiply and Add Word to Hi, Lo
MADDU|MIPS32|Multiply and Add Unsigned Word to Hi, Lo
MSUB|MIPS32|Multiply and Subtract Word to Hi, Lo
MSUBU|MIPS32|Multiply and Subtract Unsigned Word to Hi, Lo
MUL|MIPS32|Multiply Word to GPR
MULT|MIPS32|Multiply Word
MULTU|MIPS32|Multiply Unsigned Word
SEB|MIPS32R2|Sign-Extend Byte
SEH|MIPS32R2|Sign-Extend Halftword
SLT|MIPS32|Set on Less Than
SLTI|MIPS32|Set on Less Than Immediate
SLTIU|MIPS32|Set on Less Than Immediate Unsigned
SLTU|MIPS32|Set on Less Than Unsigned
SUB|MIPS32|Subtract Word
SUBU|MIPS32|Subtract Word

//CPU Branch and Jump Instructions
B|MIPS32,AI|Unconditional Branch
BAL|MIPS32,AI|Branch and Link
BEQ|MIPS32|Branch on Equal
BGEZ|MIPS32|Branch on Greater Than or Equal to Zero
BGEZAL|MIPS32|Branch on Greater Than or Equal to Zero and Link
BGTZ|MIPS32|Branch on Greater Than Zero
BLEZ|MIPS32|Branch on Less Than or Equal to Zero
BLTZ|MIPS32|Branch on Less Than Zero
BLTZAL|MIPS32|Branch on Less Than Zero and Link
BNE|MIPS32|Branch on Not Equal
J|MIPS32|Jump
JAL|MIPS32|Jump and Link
JALR|MIPS32|Jump and Link Register
JALR.HB|MIPS32R2|Jump and Link Register with Hazard Barrier
JALX|MIPS32+MIPS16e|Jump and Link Exchange
JR|MIPS32|Jump Register
JR.HB|MIPS32R2|Jump Register with Hazard Barrier
EHB|MIPS32R2|Execution Hazard Barrier
NOP|MIPS32,AI|No Operation
PAUSE|MIPS32R2|Wait for LLBit to Clear
SSNOP|MIPS32|Superscalar No Operation

//CPU Load, Store, and Memory Control Instructions
LB|MIPS32|Load Byte
LBU|MIPS32|Load Byte Unsigned
LH|MIPS32|Load Halfword
LHU|MIPS32|Load Halfword Unsigned
LL|MIPS32|Load Linked Word
LW|MIPS32|Load Word
LWL|MIPS32|Load Word Left
LWR|MIPS32|Load Word Right
PREF|MIPS32|Prefetch
SB|MIPS32|Store Byte
SC|MIPS32|Store Conditional Word
SH|MIPS32|Store Halfword
SW|MIPS32|Store Word
SWL|MIPS32|Store Word Left
SWR|MIPS32|Store Word Right
SYNC|MIPS32|Synchronize Shared Memory
SYNCI|MIPS32R2|Synchronize Caches to Make Instruction Writes Effective

//CPU Logical Instructions
AND|MIPS32|And
ANDI|MIPS32|And Immediate
LUI|MIPS32|Load Upper Immediate
NOR|MIPS32|Not Or
OR|MIPS32|Or
ORI|MIPS32|Or Immediate
XOR|MIPS32|Exclusive Or
XORI|MIPS32|Exclusive Or Immediate

//CPU Insert/Extract Instructions
EXT|MIPS32R2|Extract Bit Field
INS|MIPS32R2|Insert Bit Field
WSBH|MIPS32R2|Word Swap Bytes Within Halfwords

//CPU Move Instructions
MFHI|MIPS32|Move From HI Register
MFLO|MIPS32|Move From LO Register
MOVF|MIPS32|Move Conditional on Floating Point False
MOVN|MIPS32|Move Conditional on Not Zero
MOVT|MIPS32|Move Conditional on Floating Point True
MOVZ|MIPS32|Move Conditional on Zero
MTHI|MIPS32|Move To HI Register
MTLO|MIPS32|Move To LO Register
RDHWR|MIPS32R2|Read Hardware Register

//CPU Shift Instructions
ROTR|MIPS32R2|Rotate Word Right
ROTRV|MIPS32R2|Rotate Word Right Variable
SLL|MIPS32|Shift Word Left Logical
SLLV|MIPS32|Shift Word Left Logical Variable
SRA|MIPS32|Shift Word Right Arithmetic
SRAV|MIPS32|Shift Word Right Arithmetic Variable
SRL|MIPS32|Shift Word Right Logical
SRLV|MIPS32|Shift Word Right Logical Variable

//CPU Trap Instructions
BREAK|MIPS32|Breakpoint
SYSCALL|MIPS32|System Call
TEQ|MIPS32|Trap if Equal
TEQI|MIPS32|Trap if Equal Immediate
TGE|MIPS32|Trap if Greater or Equal
TGEI|MIPS32|Trap if Greater of Equal Immediate
TGEIU|MIPS32|Trap if Greater or Equal Immediate Unsigned
TGEU|MIPS32|Trap if Greater or Equal Unsigned
TLT|MIPS32|Trap if Less Than
TLTI|MIPS32|Trap if Less Than Immediate
TLTIU|MIPS32|Trap if Less Than Immediate Unsigned
TLTU|MIPS32|Trap if Less Than Unsigned
TNE|MIPS32|Trap if Not Equal
TNEI|MIPS32|Trap if Not Equal Immediate

//Obsolete CPU Branch Instructions
BEQL|MIPS32,OB|Branch on Equal Likely
BGEZALL|MIPS32,OB|Branch on Greater Than or Equal to Zero and Link Likely
BGEZL|MIPS32,OB|Branch on Greater Than or Equal to Zero Likely
BGTZL|MIPS32,OB|Branch on Greater Than Zero Likely
BLEZL|MIPS32,OB|Branch on Less Than or Equal to Zero Likely
BLTZALL|MIPS32,OB|Branch on Less Than Zero and Link Likely
BLTZL|MIPS32,OB|Branch on Less Than Zero Likely
BNEL|MIPS32,OB|Branch on Not Equal Likely

//FPU Arithmetic Instructions
ABS.S|MIPS32|Floating Point Absolute Value
ABS.D|MIPS32|Floating Point Absolute Value
ABS.PS|MIPS64,MIPS32R2|Floating Point Absolute Value
ADD.S|MIPS32|Floating Point Add
ADD.D|MIPS32|Floating Point Add
ADD.PS|MIPS64,MIPS32R2|Floating Point Add
DIV.S|MIPS32|Floating Point Divide
DIV.D|MIPS32|Floating Point Divide
MADD.S|MIPS64,MIPS32R2|Floating Point Multiply Add
MADD.D|MIPS64,MIPS32R2|Floating Point Multiply Add
MADD.PS|MIPS64,MIPS32R2|Floating Point Multiply Add
MSUB.S|MIPS64,MIPS32R2|Floating Point Multiply Subtract
MSUB.D|MIPS64,MIPS32R2|Floating Point Multiply Subtract
MSUB.PS|MIPS64,MIPS32R2|Floating Point Multiply Subtract
MUL.S|MIPS32|Floating Point Multiply
MUL.D|MIPS32|Floating Point Multiply
MUL.PS|MIPS64,MIPS32R2|Floating Point Multiply
NEG.S|MIPS32|Floating Point Negate
NEG.D|MIPS32|Floating Point Negate
NEG.PS|MIPS64,MIPS32R2|Floating Point Negate
NMADD.S|MIPS64,MIPS32R2|Floating Point Negative Multiply Add
NMADD.D|MIPS64,MIPS32R2|Floating Point Negative Multiply Add
NMADD.PS|MIPS64,MIPS32R2|Floating Point Negative Multiply Add
NMSUB.S|MIPS64,MIPS32R2|Floating Point Negative Multiply Subtract
NMSUB.D|MIPS64,MIPS32R2|Floating Point Negative Multiply Subtract
NMSUB.PS|MIPS64,MIPS32R2|Floating Point Negative Multiply Subtract
RECIP.S|MIPS64,MIPS32R2|Reciprocal Approximation
RECIP.D|MIPS64,MIPS32R2|Reciprocal Approximation
RSQRT.S|MIPS64,MIPS32R2|Reciprocal Square Root Approximation
RSQRT.D|MIPS64,MIPS32R2|Reciprocal Square Root Approximation
SQRT.S|MIPS32|Floating Point Square Root
SQRT.D|MIPS32|Floating Point Square Root
SUB.S|MIPS32|Floating Point Subtract
SUB.D|MIPS32|Floating Point Subtract
SUB.PS|MIPS64,MIPS32R2|Floating Point Subtract

//FPU Branch Instructions
BC1F|MIPS32|Branch on FP False
BC1T|MIPS32|Branch on FP True

//FPU Compare Instructions
C.F.S|MIPS32|Floating Point Compare
C.F.D|MIPS32|Floating Point Compare
C.F.PS|MIPS64,MIPS32R2|Floating Point Compare
C.UN.S|MIPS32|Floating Point Compare
C.UN.D|MIPS32|Floating Point Compare
C.UN.PS|MIPS64,MIPS32R2|Floating Point Compare
C.EQ.S|MIPS32|Floating Point Compare
C.EQ.D|MIPS32|Floating Point Compare
C.EQ.PS|MIPS64,MIPS32R2|Floating Point Compare
C.UEQ.S|MIPS32|Floating Point Compare
C.UEQ.D|MIPS32|Floating Point Compare
C.UEQ.PS|MIPS64,MIPS32R2|Floating Point Compare
C.OLT.S|MIPS32|Floating Point Compare
C.OLT.D|MIPS32|Floating Point Compare
C.OLT.PS|MIPS64,MIPS32R2|Floating Point Compare
C.ULT.S|MIPS32|Floating Point Compare
C.ULT.D|MIPS32|Floating Point Compare
C.ULT.PS|MIPS64,MIPS32R2|Floating Point Compare
C.OLE.S|MIPS32|Floating Point Compare
C.OLE.D|MIPS32|Floating Point Compare
C.OLE.PS|MIPS64,MIPS32R2|Floating Point Compare
C.ULE.S|MIPS32|Floating Point Compare
C.ULE.D|MIPS32|Floating Point Compare
C.ULE.PS|MIPS64,MIPS32R2|Floating Point Compare
C.SF.S|MIPS32|Floating Point Compare
C.SF.D|MIPS32|Floating Point Compare
C.SF.PS|MIPS64,MIPS32R2|Floating Point Compare
C.NGLE.S|MIPS32|Floating Point Compare
C.NGLE.D|MIPS32|Floating Point Compare
C.NGLE.PS|MIPS64,MIPS32R2|Floating Point Compare
C.SEQ.S|MIPS32|Floating Point Compare
C.SEQ.D|MIPS32|Floating Point Compare
C.SEQ.PS|MIPS64,MIPS32R2|Floating Point Compare
C.NGL.S|MIPS32|Floating Point Compare
C.NGL.D|MIPS32|Floating Point Compare
C.NGL.PS|MIPS64,MIPS32R2|Floating Point Compare
C.LT.S|MIPS32|Floating Point Compare
C.LT.D|MIPS32|Floating Point Compare
C.LT.PS|MIPS64,MIPS32R2|Floating Point Compare
C.NGE.S|MIPS32|Floating Point Compare
C.NGE.D|MIPS32|Floating Point Compare
C.NGE.PS|MIPS64,MIPS32R2|Floating Point Compare
C.LE.S|MIPS32|Floating Point Compare
C.LE.D|MIPS32|Floating Point Compare
C.LE.PS|MIPS64,MIPS32R2|Floating Point Compare
C.NGT.S|MIPS32|Floating Point Compare
C.NGT.D|MIPS32|Floating Point Compare
C.NGT.PS|MIPS64,MIPS32R2|Floating Point Compare
ALNV.PS|MIPS64,MIPS32R2|Floating Point Align Variable
CEIL.L.S|MIPS64,MIPS32R2|Floating Point Ceiling Convert to Long Fixed Point
CEIL.L.D|MIPS64,MIPS32R2|Floating Point Ceiling Convert to Long Fixed Point
CEIL.W.S|MIPS64,MIPS32R2|Floating Point Ceiling Convert to Word Fixed Point
CEIL.W.D|MIPS64,MIPS32R2|Floating Point Ceiling Convert to Word Fixed Point
CVT.D.S|MIPS32|Floating Point Convert to Double Floating Point
CVT.D.W|MIPS32|Floating Point Convert to Double Floating Point
CVT.D.L|MIPS64,MIPS32R2|Floating Point Convert to Double Floating Point
CVT.L.S|MIPS64,MIPS32R2|Floating Point Convert to Long Fixed Point
CVT.L.D|MIPS64,MIPS32R2|Floating Point Convert to Long Fixed Point
CVT.PS.S|MIPS64,MIPS32R2|Floating Point Convert Pair to Paired Single
CVT.S.PL|MIPS64,MIPS32R2|Floating Point Convert Pair Lower to Single Floating Point
CVT.S.PU|MIPS64,MIPS32R2|Floating Point Convert Pair Upper to Single Floating Point
CVT.S.D|MIPS32|Floating Point Convert to Single Floating Point
CVT.S.W|MIPS32|Floating Point Convert to Single Floating Point
CVT.S.L|MIPS64,MIPS32R2|Floating Point Convert to Single Floating Point
CVT.W.S|MIPS32|Floating Point Convert to Word Fixed Point
CVT.W.D|MIPS32|Floating Point Convert to Word Fixed Point
FLOOR.L.S|MIPS64,MIPS32R2|Floating Point Floor Convert to Long Fixed Point
FLOOR.L.D|MIPS64,MIPS32R2|Floating Point Floor Convert to Long Fixed Point
FLOOR.W.S|MIPS32|Floating Point Floor Convert to Word Fixed Point
FLOOR.W.D|MIPS32|Floating Point Floor Convert to Word Fixed Point
PLL.PS|MIPS64,MIPS32R2|Pair Lower Lower
PLU.PS|MIPS64,MIPS32R2|Pair Lower Upper
PUL.PS|MIPS64,MIPS32R2|Pair Upper Lower
PUU.PS|MIPS64,MIPS32R2|Pair Upper Upper
ROUND.L.S|MIPS64,MIPS32R2|Floating Point Round to Long Fixed Point
ROUND.L.D|MIPS64,MIPS32R2|Floating Point Round to Long Fixed Point
ROUND.W.S|MIPS32|Floating Point Round to Word Fixed Point
ROUND.W.D|MIPS32|Floating Point Round to Word Fixed Point
TRUNC.L.S|MIPS64,MIPS32R2|Floating Point Truncate to Long Fixed Point
TRUNC.L.D|MIPS64,MIPS32R2|Floating Point Truncate to Long Fixed Point
TRUNC.W.S|MIPS32|Floating Point Truncate to Word Fixed Point
TRUNC.W.D|MIPS32|Floating Point Truncate to Word Fixed Point

//FPU Load, Store, and Memory Control Instructions
LDC1|MIPS32|Load Doubleword to Floating Point
LDXC1|MIPS64,MIPS32R2|Load Doubleword Indexed to Floating Point
LUXC1|MIPS64,MIPS32R2|Load Doubleword Indexed Unaligned to Floating Point
LWC1|MIPS32|Load Word to Floating Point
LWXC1|MIPS64,MIPS32R2|Load Word Indexed to Floating Point
PREFX|MIPS32|Prefetch Indexed
SDC1|MIPS32|Store Doubleword from Floating Point
SDXC1|MIPS64,MIPS32R2|Store Doubleword Indexed from Floating Point
SUXC1|MIPS64,MIPS32R2|Store Doubleword Indexed Unaligned from Floating Point
SWC1|MIPS32|Store Word from Floating Point
SWXC1|MIPS64,MIPS32R2|Store Word Indexed from Floating Point

//FPU Move Instructions
CFC1|MIPS32|Move Control Word from Floating Point
CTC1|MIPS32|Move Control Word to Floating Point
MFC1|MIPS32|Move Word from Floating Point
MFHC1|MIPS32R2|Move Word from High Half of Floating Point Register
MOV.S|MIPS32|Floating Point Move
MOV.D|MIPS32|Floating Point Move
MOV.PS|MIPS64,MIPS32R2|Floating Point Move
MOVF.S|MIPS32|Floating Point Move Conditional on Floating Point False
MOVF.D|MIPS32|Floating Point Move Conditional on Floating Point False
MOVF.PS|MIPS64,MIPS32R2|Floating Point Move Conditional on Floating Point False
MOVN.S|MIPS32|Floating Point Move Conditional on Not Zero
MOVN.D|MIPS32|Floating Point Move Conditional on Not Zero
MOVN.PS|MIPS64,MIPS32R2|Floating Point Move Conditional on Not Zero
MOVT.S|MIPS32|Floating Point Move Conditional on Floating Point True
MOVT.D|MIPS32|Floating Point Move Conditional on Floating Point True
MOVT.PS|MIPS64,MIPS32R2|Floating Point Move Conditional on Floating Point True
MOVZ.S|MIPS32|Floating Point Move Conditional on Zero
MOVZ.D|MIPS32|Floating Point Move Conditional on Zero
MOVZ.PS|MIPS64,MIPS32R2|Floating Point Move Conditional on Zero
MTC1|MIPS32|Move Word to Floating Point
MTHC1|MIPS32R2|Move Word to High Half of Floating Point Register

//Obsolete FPU Branch Instructions
BC1FL|MIPS32,OB|Branch on FP False Likely
BC1TL|MIPS32,OB|Branch on FP True Likely

//Coprocessor Branch Instructions
BC2F|MIPS32|Branch on COP2 False
BC2T|MIPS32|Branch on COP2 True

//Coprocessor Execute Instructions
COP2|MIPS32|Coprocessor Operation to Coprocessor 2

//Coprocessor Load and Store Instructions
LDC2|MIPS32|Load Doubleword to Coprocessor 2
LWC2|MIPS32|Load Word to Coprocessor 2
SDC2|MIPS32|Store Doubleword from Coprocessor 2
SWC2|MIPS32|Store Word from Coprocessor 2

//Coprocessor Move Instructions
CFC2|MIPS32|Move Control Word from Coprocessor 2
CTC2|MIPS32|Move Control Word to Coprocessor 2
MFC2|MIPS32|Move Word from Coprocessor 2
MFHC2|MIPS32R2|Move Word from High Half of Coprocessor 2 Register
MTC2|MIPS32|Move Word to Coprocessor 2
MTHC2|MIPS32R2|Move Word to High Half of Coprocessor 2 Register

//Obsolete Coprocessor Branch Instructions
BC2FL|MIPS32,OB|Branch on COP2 False Likely
BC2TL|MIPS32,OB|Branch on COP2 True Likely

//Privileged Instructions
CACHE|MIPS32|Perform Cache Operation
DI|MIPS32R2|Disable Interrupts
EI|MIPS32R2|Enable Interrupts
ERET|MIPS32|Exception Return
MFC0|MIPS32|Move from Coprocessor 0
MTC0|MIPS32|Move to Coprocessor 0
RDPGPR|MIPS32R2|Read GPR from Previous Shadow Set
TLBP|MIPS32|Probe TLB for Matching Entry
TLBR|MIPS32|Read Indexed TLB Entry
TLBWI|MIPS32|Write Indexed TLB Entry
TLBWR|MIPS32|Write Random TLB Entry
WAIT|MIPS32|Enter Standby Mode
WRPGPR|MIPS32R2|Write GPR to Previous Shadow Set

//EJTAG Instructions
DERET|MIPS32,EJTAG|Debug Exception Return
SDBBP|MIPS32,EJTAG|Software Debug Breakpoint