[fpc-devel] BBB / PRUS / M3 and fpc

Michael Schnell mschnell at lumino.de
Fri Jul 5 14:19:45 CEST 2013

On 07/05/2013 02:09 PM, Mark Morgan Lloyd wrote:
> Apparently there's a kernel module to handle the loading, 
Seems great. (see my other mail.)

> but the sticking point might be that each coprocessor has a limited 
> code space (8K?).
The PRUS features:
  - 8 K instruction memory for each processor
  - 8 K data memory for each processor
  - 12 K shared memory (common for both processors)

So this of course is rather limited.

But the processors can access any memory address of the chip (internal 
and external RAM and peripherals) through bus bridges. I don't know if 
the M3s are strictly limited to fetch instructions from their 
instructions RAM or if this is just the fastest (zero wait states) source.


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