[fpc-devel] SMP > 2 core Cache issue with Posix threads

[Andrew Brunner]

On Fri, Jul 1, 2011 at 8:51 AM, Mark Morgan Lloyd
<markMLl.fpc-devel at telemetry.co.uk> wrote:
> Fair play, he /has/ said he's mailed Andrew looking for source.

I never received such email.  But to Michael's defense, Google mail
isn't the product it once was.

> However under the circumstances we've got to have something definitive to
> inspect and test- I for one would be very unhappy if I spent my time running
> up a rarely-used system and updating its compiler, only to be told that I
> didn't have the right version of the test program.

I did all of my research on memory barriers a while ago.  The best
site that describes this "phenomena" is
http://en.wikipedia.org/wiki/Memory_barrier

There are others here that helped walk me through this a while ago,
but to me, this is a non-issue.  I intend to use interlocked
statements for mission critical memory assignments.

I would suggest the poster do more questions than suggest there is a
problem with either FPC, POSIX, or pthreads implementations, or kernel
bugs, or OOP principals regarding inter-thread memory access to LCL
objects.  Anyone designing systems should already know how to employ
techniques.