[fpc-devel] threadvar implementation
mschnell at lumino.de
Thu Aug 5 10:01:42 CEST 2010
On 08/04/2010 09:19 PM, Hans-Peter Diettrich wrote:
> Michael Schnell schrieb:
>> Look at the document I mentioned: a "linear address" is 48 bits,
>> while a pointer is only 32 bits (the "Offset") .
> Read section 3.3 ff. and 3.8.
> Linear addresses are always 32 bit, and only a few server-type CPUs
> had *physical* addresses of 36 bits, using PAE or PSE.
Figure 3-5 in the document (
http://flint.cs.yale.edu/cs422/doc/24547212.pdf ) clearly states that
the "Logical Address" is 48 Bits. This is what the "Linear address" is
During each instruction execution first a 48 Bit "Logical Address" is
calculated and the hardware constructs a 32 bit logical address from same.
So to understand (or define) what an ASM instruction actually does, it's
necessary to look at the "Logical Address" it deals with. Same is always
constructed using segment registers and therefor influenced by the flags
that might be set by a preceding "segment prefix" instruction.
An exception seems to be the the "LEA" instruction that just ignores the
"Seg. Selector" part (upper 16 bits) of the Logical Address and just
works with the "Offset" part (lower 32 bits) of the Logical Address,
thus assuming the same "Seg. Selector" (whichever !) as well for the
target as for the source.
The "Physical Address" is independent of segment registers and comes
into play later in the process, introduced by the MMU, which in fact is
"outside" of the CPU core.
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