[fpc-devel] threadvar implementation

Michael Schnell mschnell at lumino.de
Thu Aug 5 09:49:27 CEST 2010

  OK I was wrong by two bits.

See http://flint.cs.yale.edu/cs422/doc/24547212.pdf page 3-7

The "logical address" is 24 bits: 16 bits "Segment Selector" and 32 bits 
"Offset". Obviously in an instruction, usually the "Segment Selector" is 
taken from one of the six Segment registers while the "Offset" is 
calculated in the Instruction from a constant and/or some register(s). 
Which Segment register is to be used is determined by the instruction 
(either DS or SS) and can be changed by the use of a prefix (*).

The Selector is used to take one of up to 2^13 "Segment Descriptor"s out 
of a set of two Descriptor tables. So there are up to 2^14 = 16,384 
(and not 64 K as I assumed) such "Segment Descriptors". (Obviously much 
less are actually used practically.)

The (64 bit sized) Segment Descriptor provides a 32 bit "Base Address".

The final "Linear Address" is calculated by adding the Offset to this 
"Base Address"

This in fact allows for using a max of 16,384 Segments, each 4 GByte 
sized at max, but limited by a size given in the Segment Descriptor.

These Segments can overlap, but theoretically 16,384 non overlapping 
segments can be constructed. In this case of course they can't be 4 
GByte each,

Of course all this is hardware, disregarding what limits any OS might 


(*)                                     "For virtually any kind of program
execution to take place, at least the code-segment (CS), data-segment 
(DS), and stack-segment
(SS) registers must be loaded with valid segment selectors. The 
processor also provides three
additional data-segment registers (ES, FS, and GS), which can be used to 
make additional data
segments available to the currently executing program (or task)."

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