[fpc-devel] Issue with Compiler output for shr on Cortex-M4

[Michael Ring]

Your patch did the trick, assembler Code is looking good now:

    pByte(@DR)^ := (aWord shr 8);
      0800 187E  LDR          R0, [R11, #-0x38]
      0800 1882  ADD.W        R1, R0, #0xC
      0800 1886  LDRH         R0, [R11, #-0x30]
      0800 188A  UXTB         R0, R0, ROR #8
      0800 188E  STRB         R0, [R1]

and my application also works fine now.


This is a small demo of the issue:

program shlissue;
var
   MemoryAddress : pointer;
   aWord : word;
begin
   aWord := $1000;
   pByte(MemoryAddress)^ := aWord shr 8;
end.

This compiles fine with your patch, shows the issue when compiled with 
unpatched fpc trunk

Strange that you could not see the issue with -O1

I have also included an lpi file. When I open the lpi file in Lazarus it 
shows me optimizations set as O1. When I call lazbuild with --verbose 
then I get:

CmdLine="/usr/local/bin/fpc  -Tembedded -Parm -MObjFPC -Scgi -Ch8192 
-Cs8192 -O1 -gw2 -l -vewnhibq -Fi/Users/ring/devel/mbf/Source 
-Fi/Users/ring/devel/mbf/Samples/shlissue/lib/arm-embedded 
-Fu/Users/ring/devel/mbf/Source 
-Fu/Users/ring/devel/mbf/Samples/shlissue/ 
-FU/Users/ring/devel/mbf/Samples/shlissue/lib/arm-embedded/ 
-FE/Users/ring/devel/mbf/Samples/shlissue/ 
-o/Users/ring/devel/mbf/Samples/shlissue/shlissue -Cparmv7em 
-XParm-none-eabi- -Wpnucleof401re -dnucleof401re shlissue.lpr"


Thany you (again and again) for your help!


Michael


Am 05.02.19 um 21:09 schrieb Jeppe Johansen:
> I can only reproduce this with peephole optimization turned on (O2). 
> Can you share more code that reproduces it?
>
> Either way here's a patch that might fix it?
>
> Best Regards,
> Jeppe
>
> On 2/3/19 5:31 PM, Michael Ring wrote:
>
>> Forgot to mention I am using Trunk compiler from today revision 41187 
>> ond optimization level was -O1
>>
>> Michael
>>
>> Am 03.02.19 um 17:20 schrieb Michael Ring:
>>> I think I found another issue with Code generation, this time on 
>>> Cortex-M4:
>>>
>>> I need to write Byte Aligned to the Data Register of the SPI 
>>> Interface of a STM32 Chip....
>>>
>>> so what I (try) to do is:
>>>
>>> using pByte(@DR)^ to force a single byte transfer and I succeed with 
>>> the byte alignment.......
>>>
>>> BUT
>>>
>>> please check the generated assembler, the requirred LSRS (SHR) is 
>>> not done by the compiler.
>>>
>>> Just for fun I removed the byte alignment and the LSRS shows up...
>>>
>>> @Jeppe, can this have to do with the fix for Cortex-M0 you provided 
>>> to me a few days ago or is this just another issue?
>>>
>>>     pByte(@DR)^ := aWord shr 8;
>>>      0800 185A  LDR          R0, [R11, #-0x38]
>>>      0800 185E  ADD.W        R1, R0, #0xC
>>>      0800 1862  LDRH         R0, [R11, #-0x30]
>>>      0800 1866  STRB         R0, [R1]
>>>
>>>     DR := aWord shr 8;
>>>      0800 1868  LDRH         R0, [R11, #-0x30]
>>>      0800 186C  LSRS         R1, R0, #8
>>>      0800 186E  LDR          R0, [R11, #-0x38]
>>>      0800 1872  STR          R1, [R0, #0xC]
>>>
>>> Thank you,
>>>
>>>
>>> Michael
>>>
>>> _______________________________________________
>>> fpc-devel maillist  -  fpc-devel at lists.freepascal.org
>>> http://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel
>>
>
> _______________________________________________
> fpc-devel maillist  -  fpc-devel at lists.freepascal.org
> http://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freepascal.org/pipermail/fpc-devel/attachments/20190206/c958368f/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: shlissue-nucleof401re.lpi
Type: text/xml
Size: 1259 bytes
Desc: not available
URL: <http://lists.freepascal.org/pipermail/fpc-devel/attachments/20190206/c958368f/attachment.xml>