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<p>Your patch did the trick, assembler Code is looking good now:</p>
<p> pByte(@DR)^ := (aWord shr 8);<br>
0800 187E LDR R0, [R11, #-0x38]<br>
0800 1882 ADD.W R1, R0, #0xC<br>
0800 1886 LDRH R0, [R11, #-0x30]<br>
0800 188A UXTB R0, R0, ROR #8<br>
0800 188E STRB R0, [R1]<br>
</p>
<p>and my application also works fine now.</p>
<p><br>
</p>
<p>This is a small demo of the issue:<br>
</p>
<p>program shlissue;<br>
var<br>
MemoryAddress : pointer;<br>
aWord : word;<br>
begin<br>
aWord := $1000;<br>
pByte(MemoryAddress)^ := aWord shr 8;<br>
end.<br>
</p>
<p>This compiles fine with your patch, shows the issue when compiled
with unpatched fpc trunk</p>
<p>Strange that you could not see the issue with -O1</p>
<p>I have also included an lpi file. When I open the lpi file in
Lazarus it shows me optimizations set as O1. When I call lazbuild
with --verbose then I get:</p>
<p>CmdLine="/usr/local/bin/fpc -Tembedded -Parm -MObjFPC -Scgi
-Ch8192 -Cs8192 -O1 -gw2 -l -vewnhibq
-Fi/Users/ring/devel/mbf/Source
-Fi/Users/ring/devel/mbf/Samples/shlissue/lib/arm-embedded
-Fu/Users/ring/devel/mbf/Source
-Fu/Users/ring/devel/mbf/Samples/shlissue/
-FU/Users/ring/devel/mbf/Samples/shlissue/lib/arm-embedded/
-FE/Users/ring/devel/mbf/Samples/shlissue/
-o/Users/ring/devel/mbf/Samples/shlissue/shlissue -Cparmv7em
-XParm-none-eabi- -Wpnucleof401re -dnucleof401re shlissue.lpr"</p>
<p><br>
</p>
<p>Thany you (again and again) for your help!</p>
<p><br>
</p>
<p>Michael</p>
<p><br>
</p>
<div class="moz-cite-prefix">Am 05.02.19 um 21:09 schrieb Jeppe
Johansen:<br>
</div>
<blockquote type="cite"
cite="mid:b7723cc4-5401-e54d-4cd2-3e9917744eac@j-software.dk">I
can only reproduce this with peephole optimization turned on (O2).
Can you share more code that reproduces it?
<br>
<br>
Either way here's a patch that might fix it?
<br>
<br>
Best Regards,
<br>
Jeppe
<br>
<br>
On 2/3/19 5:31 PM, Michael Ring wrote:
<br>
<br>
<blockquote type="cite">Forgot to mention I am using Trunk
compiler from today revision 41187 ond optimization level was
-O1
<br>
<br>
Michael
<br>
<br>
Am 03.02.19 um 17:20 schrieb Michael Ring:
<br>
<blockquote type="cite">I think I found another issue with Code
generation, this time on Cortex-M4:
<br>
<br>
I need to write Byte Aligned to the Data Register of the SPI
Interface of a STM32 Chip....
<br>
<br>
so what I (try) to do is:
<br>
<br>
using pByte(@DR)^ to force a single byte transfer and I
succeed with the byte alignment.......
<br>
<br>
BUT
<br>
<br>
please check the generated assembler, the requirred LSRS (SHR)
is not done by the compiler.
<br>
<br>
Just for fun I removed the byte alignment and the LSRS shows
up...
<br>
<br>
@Jeppe, can this have to do with the fix for Cortex-M0 you
provided to me a few days ago or is this just another issue?
<br>
<br>
pByte(@DR)^ := aWord shr 8;
<br>
0800 185A LDR R0, [R11, #-0x38]
<br>
0800 185E ADD.W R1, R0, #0xC
<br>
0800 1862 LDRH R0, [R11, #-0x30]
<br>
0800 1866 STRB R0, [R1]
<br>
<br>
DR := aWord shr 8;
<br>
0800 1868 LDRH R0, [R11, #-0x30]
<br>
0800 186C LSRS R1, R0, #8
<br>
0800 186E LDR R0, [R11, #-0x38]
<br>
0800 1872 STR R1, [R0, #0xC]
<br>
<br>
Thank you,
<br>
<br>
<br>
Michael
<br>
<br>
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<br>
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<br>
</blockquote>
<br>
</blockquote>
<br>
<fieldset class="mimeAttachmentHeader"></fieldset>
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