[fpc-pascal] Broken code with PEEPHOLE & REGVAR

[Peter]

On 12/03/2022 11:33, Florian Klämpfl via fpc-pascal wrote:
>
>> Am 12.03.2022 um 12:05 schrieb Peter via fpc-pascal <fpc-pascal at lists.freepascal.org>:
>>
>> Its looking like it was fixed in main somewhere between
>>
>> 31cd3df7    24 Jan, 2021
>> &
>> 837b433a    28 Apr, 2021
> Can you bisect it by any chance? See https://wiki.freepascal.org/FPC_git#bisect.27ing
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Hi Florian,

The problem was fixed with commit 503fc85d
   2021-04-06 florian  * patch by J. Gareth Moreton: handle register allocations correctly in MovMov2Mov 3, resolves #38703

https://gitlab.com/freepascal.org/fpc/source/-/issues/38703


Assembler for line 587 and surrounding comments from previous commit

# Peephole Optimization: MovMov2Mov 3 done
# Peephole Optimization: MovMovMov2MovMov 1 done
# [587] TestLoc := AttackLoc;
     movl    83288(%rsp),%eax
# Var AttackLoc located in register r13d
     movl    %eax,24(%rsp)
# Peephole Optimization: MovxMov2Movx


 From commit 503fc85d 2021-04-06

# Peephole Optimization: MovMov2Mov 3 done
# [587] TestLoc := AttackLoc;
     movl    83288(%rsp),%r13d
# Var AttackLoc located in register r13d
# Peephole Optimization: MovMov2MovMov1 done
     movl    %r13d,24(%rsp)


In this example, although the compiler intends to use r13d for the parameter AttackLoc from line 587 onwards,
it does not actually load that register, prior to fix for #38703



Cheers,
Peter