[fpc-pascal] Is RV32I instruction set for RISC-V (embedded) supported?

[Florian Klämpfl]

Am 05.03.21 um 10:41 schrieb Bernd Mueller via fpc-pascal:
> Hello,
> 
> I would like to use fpc to program a FPGA softcore RISC-V cpu. The
> softcore has the RV32I instruction set implemented.
> 
> I modified the Makefile in rtl/embedded, so that the known SUBARCH
> rv32imac replaces the option -Cprv32imac with now -Cprv32i.  But this
> leads to the following error message, when I try to compile the
> crosscompiler/rtl:
> 
> /home/bernd/fpc/fpc331/48875/src/compiler/ppcrossrv32 -Ur -Cprv32i
> -Tembedded -Priscv32 -XPriscv32-embedded- -Ur -Xs -O2 -n -Fi../inc
> -Fi../riscv32 -FE.
> -FU/home/bernd/fpc/fpc331/48875/src/rtl/units/riscv32-embedded
> -Fl/home/bernd/riscv/riscv_2008/lib/gcc/riscv64-unknown-elf/10.1.0/rv64imafdc/lp64d 
> 
> -driscv32 -dRELEASE -al  -Us -Sg system.pp @system.cfg
> /home/bernd/fpc/fpc331/48875/src/rtl/units/riscv32-embedded/system.s:
> Assembler messages:
> /home/bernd/fpc/fpc331/48875/src/rtl/units/riscv32-embedded/system.s:39578:
> Error: unrecognized opcode `mul x11,x11,x10'
> 
> Is this expected, since RV32I is not supported, or should this work?

It is not expected that it works as RiscV support is still work in 
progress, but it should work ;) I'll look into it.