[fpc-pascal] FPC embedded ?

Marco van de Voort marcov at stack.nl
Thu Mar 5 12:34:10 CET 2015

In our previous episode, Michael Schnell said:
> > the next generation will have TCP/IP (using wiznet w5500)
> AFAIK there are PIC32 chips with MAC on board so you just need a small 
> PHY chip (or a switch chip).

I've used such solutions in the past, but actually I'm quite happy with
the current situation. I would probably even use it with another chip.

Simply because the whole manage of the chip is asynchronous and all data
transfers (including their commands/register writes) is DMAd, and the rest
is buffered spi and you can set masks to only get interrupts for certain
destination IP and ports. Packets transfer with less than 5us CPU time.

So all packets transfer actually matter, which eliminates having to
continuously transfer ethernet header to block out windows machines SMB
chatter.  (I'm really sure that our controller will never be elected master

We haven't migrated to pic32 yet because 
(1) we are only doing relative moderate extensions to current boards atm. 
    e.g. the ethernet experiments run on the expansion port of the current
    production board.  Since TCP/IP means there are only 5-6 pins used,
    bringing it to production is relatively minor
(2) we haven't seen a device with QEI yet. Maybe it is integrated ability 
in the motor control peripheral though, and as such not specified separately.
Haven't researched deeper.

The MZ's slow roll out and long erata lists haven't helped with that
 (final silicon of the revision in june I hear).

> The Library that is available by microchip for free features an 
> "embedded" TCP/IP stack supports both variants out of the box.

The w5200 is too. (you can download the relevant files from the wiznet
site). We adapted to w5500 ourselves (which is actually a lot simpler since
its memory model is simplified and addresses auto-wrap around)  

And more importantly, the provided examples actually uses DMA, while the
standard tcp/ip stack of microchip always transfers packets by manually
stuffing data into SPI registers in a while loop.  From what I saw they
don't even use enhanced buffer mode.

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