[fpc-other] Re: SMP > 2 core Cache issue with Posix threads

[Mark Morgan Lloyd]

Jonas Maebe wrote:

> And the discussion is now again at exactly the same point as the previous thread that I stopped (about low-level multithreading programming concepts). Unless someone can post code that demonstrates an actual problem with the compiler or RTL, there is no use to keep posting speculation about how a potential bug in the compiler or RTL could cause this kind of behaviour (you could start such a discussion about any bug in any person's program, claiming that it might be caused by the compiler/RTL and then endlessly continue discussing related topics without ever getting a step closer to actually discussing the compiler/RTL itself). Hence it's off topic for the fpc-devel list.

I for one would be interested to see if I could duplicate the problem on 
a medium-sized SPARC system, it is by no means impossible that there is 
an implementation problem in the cache handling of a swathe of PC 
chipsets. And if proven that would be big news.

There's precedent: some might remember the number of systems that 
wouldn't run OS/2 reliably unless their cache was disabled. And just as 
OS/2 exercised the cache in ways that DOS and Windows didn't, we have to 
remember that Delphi and FPC have long been ahead of other development 
tools in encouraging programmers to multithread.

-- 
Mark Morgan Lloyd
markMLl .AT. telemetry.co .DOT. uk

[Opinions above are the author's, not those of his employers or colleagues]