[fpc-devel] Apple M1 processor

[Jonas Maebe]

On 2021-02-09 23:30, C Western via fpc-devel wrote:
> I have located a possible fix; however I don't understand why I need
> to make the change I did. The variable reads/writes of concern
> currently use SetEvent in one thread and WaitFor in another - do
> these  not have implicit  memory barriers in them? Or is an explicit
> memory barrier required in AArch64? (or it could also be a different
> issue).

Thread synchronisation primitives like SetEvent/WaitFor indeed also 
serve as memory barriers, so  no extra barriers are required.


Jonas