[fpc-devel] Support for AVR subarch avrxmega3 (megaAVR 0, tinyAVR 0/1 series)
christo.crause at gmail.com
Sun Jan 19 08:20:03 CET 2020
I would like to offer support for the relatively new AVR 8-bit
subarchitecture avrxmega3 which includes the following series: megaAVR 0,
tinyAVR 0 and 1. This adds 35 new controllers to FPC's repertoire. The
current state can be viewed in a git branch (
https://github.com/ccrause/freepascal/tree/avrxmega3). I can also prepare
a patch (perhaps two: compiler and rtl separately) if it is accepted into
There are very few differences between the classical avr8 and this new
architecture. The only differences I have picked up and included in the
compiler so far:
* Memory map excludes core register file, so I/O register addresses start
at offset 0.
* 16-bit I/O register read/write order is different. Both read and write
operations should access low register first.
Notes on controller units:
* Some interrupt names have aliases, I don't know how to specify an alias
for interrupt vectors so I picked the first name in the device file.
* The I/O registers are grouped per peripheral, this naturally leads to
using records to group the individual registers. There are a whole bunch
of bit names with clashes between registers. To work around name clashes I
decided to use objects and included the named bits inside the objects. An
example of writing named bits to a register:
ADC0.CTRLC := TADC.SAMPCAPbm or TADC.REFSEL_VDDREF or TADC.PRESC_DIV256;
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