[fpc-devel] TThread.Terminate;

Martin Frb lazarus at mfriebe.de
Sat Aug 22 17:52:21 CEST 2020

On 22/08/2020 17:39, Martin Frb via fpc-devel wrote:
> Is there some really good article (better than the wikipedia 
> https://en.wikipedia.org/wiki/Memory_barrier) on
> - memory barrier
> vs
> - cache coherency
> vs
> interlocked
> ?

 From what I found: 

Cache should update between all cores (and cpu?), and therefore threads 
should have up to date values.
Well, almost.
Apparently there can be tiny bits of a lag, sometimes.

Memory barriers will (among other things) remove that lag.

Leaves the question, if it is enough if one thread issued the barrier?

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