[fpc-devel] Error building xtensa rtl

[Christo Crause]

On Wed, Apr 1, 2020 at 12:06 AM Sven Barth <pascaldragon at googlemail.com>
wrote:

> Christo Crause <christo.crause at gmail.com> schrieb am Di., 31. März 2020,
> 19:45:
>
>> On Tue, Mar 31, 2020 at 7:39 AM Sven Barth via fpc-devel <
>> fpc-devel at lists.freepascal.org> wrote:
>>
>>> Am 30.03.2020 um 22:07 schrieb Christo Crause via fpc-devel:
>>>
>>> I've noticed GCC uses the SLLI + SRAI instructions to perform sign
>>> extension on ESP8266.
>>>
>>> Since different CPUs can support different subsets of the Xtensa
>>> instructions do you think a finalizecode type function can be used as a
>>> post code generation step to map unsupported instructions to alternative
>>> sequences?
>>>
>>>
>>> These are simply different CPU types (-CpXXX or selected by the
>>> controller type) which the code generator will handle accordingly. Just
>>> like it's done with ARM, AVR and all other platforms.
>>>
>>
>> Attach please find a patch to rtl/embedded/MakeFile* to handle subarch
>> similar to avr and others.
>>
>
> Did you manually edit the Makefile or regenerate it from the Makefile.fpc?
> If the former then your changes at the top will be overwritten by the next
> makefile regeneration.
>

I directly edited the makefile to demonstrate the principle. In addition to
a change to makefile.fpc an update to fpcmake.ini is also required, see
attached fpcmake.patch


> Also attached a patch that checks whether the SEXT instruction is
>> available for the current subarchitecture, else it generates SLLI + SRAI
>> combination.
>>
>
> If SLLI and SRAI are supported by the other processors supported by FPC
> then you don't need to check for the processor type, checking against the
> capability for SEXT is enough. If some processor does not support SLLI or
> SRAI either then this would need to be a capability as well.
>

Good idea, the alternative instructions are part of the core ISA so it
should always be supported.
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