[fpc-devel] "Blank slate" next version of FPC

[J. Gareth Moreton]

 Indeed, most of the instructions for bit extracting appeared later for SSE
and AVX.  I did find one instruction that works with general-purpose
registers, named BEXTR, but it only extracts contiguous bits and requires
BMI1.

 Gareth aka. Kit

 On Sat 23/02/19 10:27 , Jonas Maebe jonas at freepascal.org sent:
 On 23/02/2019 01:30, J. Gareth Moreton wrote: 
 > Given that the reference is an offset from %rbp, the compiler will know 
 > for sure that the variable is local, so there won't be any problems with

 > multi-threading that prevents a lot of temporary register storage for 
 > safety reasons. 

 Unpacking records could be done if their address is not taken anywhere. 
 The compiler already supports keeping records in registers under the 
 same conditions, but only up to a certain size (two native registers) 
 and only using the same layout as they would have in memory (so no 
 explicit splitting out fields into separate registers). 

 On x86, it does this less often than on other architectures, because 
 that architecture does not have efficient instructions to extract/insert 
 bits from/into registers. However, one improvement that could be made 
 there in the compiler is to ignore this fact if every field of the 
 record already corresponds to exactly one register. 

 Jonas 
 _______________________________________________ 
 fpc-devel maillist - fpc-devel at lists.freepascal.org [1] 
 http://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel
[2]">http://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel 

 

Links:
------
[1] mailto:fpc-devel at lists.freepascal.org
[2] http://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freepascal.org/pipermail/fpc-devel/attachments/20190223/076deb5f/attachment.html>