[fpc-devel] Issue with Compiler output for shr on Cortex-M4

Michael Ring mail at michael-ring.org
Sun Feb 3 17:20:31 CET 2019

I think I found another issue with Code generation, this time on Cortex-M4:

I need to write Byte Aligned to the Data Register of the SPI Interface 
of a STM32 Chip....

so what I (try) to do is:

using pByte(@DR)^ to force a single byte transfer and I succeed with the 
byte alignment.......


please check the generated assembler, the requirred LSRS (SHR) is not 
done by the compiler.

Just for fun I removed the byte alignment and the LSRS shows up...

@Jeppe, can this have to do with the fix for Cortex-M0 you provided to 
me a few days ago or is this just another issue?

     pByte(@DR)^ := aWord shr 8;
      0800 185A  LDR          R0, [R11, #-0x38]
      0800 185E  ADD.W        R1, R0, #0xC
      0800 1862  LDRH         R0, [R11, #-0x30]
      0800 1866  STRB         R0, [R1]

     DR := aWord shr 8;
      0800 1868  LDRH         R0, [R11, #-0x30]
      0800 186C  LSRS         R1, R0, #8
      0800 186E  LDR          R0, [R11, #-0x38]
      0800 1872  STR          R1, [R0, #0xC]

Thank you,


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