[fpc-devel] Guidance for code generation for shift operations for AVR target

[Christo Crause]

On Mon, Aug 19, 2019 at 10:36 PM Florian Klaempfl <florian at freepascal.org>
wrote:

> Am 19.08.2019 um 22:20 schrieb Christo Crause:
> > I'm interested in trying to improve the code generated for shift
> > operations (in particular involving a compile time constant shift) for
> > the AVR target.
> For me the idea looks good, actually, I planned once to do the same, but
> got stuck for time reasons with the beginnings you discovered.
>

Attached a patch that optimizes SHL and SHR for constant right value for
comment.  Note that I haven't implemented support for SAR, ROL or ROR,
these operations should fall through to the current code path.  A heuristic
to decide when loop unrolling is favoured is also included, taking into
account -Os.  Some of the details behind the optimizations are discussed
here:
https://github.com/ccrause/freepascal/wiki/Optimizing-code-generation-for-shift-with-compile-time-constant

One remaining optimization I would like to implement is to eliminate
loading part of a variable to a register if it is eliminated by the shift
amount.  The loading of the variable and saving of the result from/to
memory happens before tcgavr.a_op_const_reg_reg gets called.  Is there a
way to remove such a redundant load instruction from
tcgavr.a_op_const_reg_reg?  Or at least mark it for removal at a later
stage ( peephole optimizer)?

I assume it would make sense to also include SAR support in this patch,
since it could be generated by div?

best wishes,
Christo
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