[fpc-devel] AVR assembler code consistency checking

[Florian Klämpfl]

Am 03.01.2018 um 15:48 schrieb Christo:
> I'm trying to implement some error checking for assembler code for the AVR target (e.g. issues
> 32007, 32109 and 32261).  After stepping through the compiler code a couple of times it seems as
> if there isn't a proper assembler constraint check build into the GAS parser in fpc. 

No. This is indeed left to the assembler.

> 
> The constraint checking I'm referring to is for example:
> sbiw R18, 1  // R18 not a legal register - sbiw only operates on registers R24, R26, R28 & R30
> cp R18, 20   // 20 not a legal register, cp operates on 2 registers only
> breq l1      // check that -64 < l1 offset < 64 and raise error if in assembler block
> 
> It seems as if some basic checking is being done in aasmcpu.pas procedure finalizeavrcode, 

This method is used to fix up code generated by the compiler.

> but
> this operates on instructions generated both by assembler blocks and regular code.  I've started
> adding some checks to finalizeavrcode procedure, but it seems clunky to me.  Is there a better
> location in the compiler to implement some assembler consistency checks?

fpc/compiler/avr/raavar.pas:TAVRInstruction.ConcatInstruction

> 
> Also, how do I manage/add new compiler error messages for these checks?

Add them to fpc/compiler/errore.msg, run make msg