[fpc-devel] bitwise shift oddity a << b

Ewald ewald at yellowcouch.org
Tue May 19 17:31:35 CEST 2015

On 05/19/2015 04:36 PM, Adriaan van Os wrote:
> But, of course, I understand that CPUs implement it wrong and that the
> compilers writers want to be compatible with the CPU doing it wrong.
> That is probably the most practical solution. But that doesn't make it
> less ludicrous.

Fast N-bit shifters (where N is a stored value in a register) are
implemented in full parallel using multiplexers. The issue with that
topology is that it doesn't scale well to large bit-widths: a shifter
allowing for 64 shifts at once needs twice as many logic as a shifter
only allowing 32 shifts at once. More logic = more time needed = more
power consumption = more resources needed. So, making "the common case"
fast (where N is a low number), simple logic dictates a smaller, simpler
shifter - nothing wrong with that.

So in those few rare cases where you actually want to shift something 42
bits, do it in two operations, manually. I do agree code can become
messy when targeting multiple platforms, but that is, IMHO, a logical
difference between platforms, just like floating point arithmetic: using
SSE instructions instead of the x87 instruction set, different results
are obtained (and that is the /same/ platform :-) ).


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