[fpc-devel] Re. z370 Cross Compilation, Pass 2 of ....
bernd.oppolzer at t-online.de
Sun Sep 1 20:21:51 CEST 2013
Am 01.09.2013 19:40, schrieb Mark Morgan Lloyd:
> At this point I'd throw in that one of the things the higher levels of
> the compiler knows is the overall properties of the registers, i.e.
> things like which ones are available for procedure parameters. This is
> one of the things that the lower level has to specify, so the
> lower-level units aren't there solely to do a macro-style substitution
> converting the compiler's internal representation to a sequence of
> assembler lines.
> The corollary of this is that it's fairly common for a new target CPU
> to necessitate higher-level changes, and these then have to be
> propagated to all of the other targets. Which is why it's important to
> keep people like Florian and Jonas happy :-)
ok, so to keep Florian, Jonas and Sven (and others) happy,
I would like to tell you that I am deeply impressed by the great
work you all have done here.
I appreciate that you discuss those things with me, and I'd like
to discuss things a little further, because before investing time
here, I would like to know as much as possible about the environment.
The last few hours gave me much insight. Thank you for that.
As I understand it now, we have several levels of the compiler:
a) scanning and parsing the source code, which leads to a "tree
of the units, which IMO is a kind of in-storage-representation of the
(and tables etc.), without much dependencies of the target, if any. I
that informations about available registers etc. of the target machine
at this level.
b) the "tree representation" is translated into a "linear assembly
list", which is
target specific; from previous posts it sounds as if there are generic
which help with this, and those methods of course need information about
target platform - but there is no "intermediate language" at this stage
in the P-Code case. (I know of other compilers, namely the IBM commercial
ones, which translate in this stage for an abstract target machine which
an arbitrary number of registers, and the later "real" code generator
down to the real number, for example 16, and the missing registers are
simulated in storage). This needs to be examined more.
c) the "linear assembly list" is written to files, more or less without
d) the files are assembled using an external assembler (in our case);
it must be callable from the FPC compiler. There exists an interface for
interfaces to other assemblers have to be built.
e) in the same way an external linker is used to link the units together.
Is this correct so far?
I'm not sure if and when I will find the time to jump really into this
doing real work,
but anyway: if we discuss these things now, it will remain in the
archives of the mailing
list and if others (like for example Paul Robinson) read this, they
don't have to
discuss it again. So IMO it's useful anyway.
Thank you, kind regards
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