[fpc-devel] Is target mips-embedded possible / planned?

[Michael Schnell]

On 02/15/2013 10:14 AM, Marco van de Voort wrote:
> Pity that they have a five stage pipeline though. Though the 16-bit lines now have
> more stalls too (the "e" series is further away from the 1 clock one 1
> instruction principle than the "f" was).
I suppose the design goal was using as little hardware as possible (for 
price and power consumption) rather than providing better speed. 
Otherwise they should have been going for ARM instead of MIPS.
> but we decided to stick with 16-bit instead.
>
Same here for the moment, as we are not yet actively planning a "high 
memory" controller based on PIC.

-Michael