[fpc-devel] x86ins.dat

[Torsten]

Hi,

Am 07.01.2012 15:01, schrieb Sergei Gorelkin:
> 07.01.2012 16:53, tgrundke пишет:
>> Hi,
>>
>> i am working on the AVX-support for the fp-compiler.
>>
>> Some AVX-assembler instructions have 4 operant e.g.
>>
>>
>> VBLENDVPD xmm1, xmm2, xmm3/m128, xmm4
>>
>>
>>
>> INTEL Def.
>>
>> 3.1.1.2 Opcode Column in the Instruction Summary Table (Instructions
>> with VEX prefix)
>>
>> /is4: An 8-bit immediate byte is present containing a source register 
>> specifier in
>> imm[7:4] and instruction-specific payload in imm[3:0].
>>
>>
>>
>> I need a idea, how can i encode (in file x86ins.dat)  the 4th operant.
>>
>> My idea:
>>
>> new flag \77 =>> 4th operand is coded in bit 4-7 and the follow byte 
>> define the bits 0-3
>> e.g.
>>
>> [VBLENDVPD]
>> (Ch_All, Ch_None, Ch_None)
>> xmmreg,xmmreg,xmmrm,xmmreg                  
>> \361\362\372\1\x4B\75\120\77\x00
>> AVX,SANDYBRIDGE
>>
>> \ 361 = prefix 066h for SSE instruction
>> \ 362 = new flag VEX (starting with 0xC5 or 0xC4)
>> \ 372 = new flag VEX-CODE include prefix 0x0F3A
>> \ 75   = VEX-BYTE contains operand no. 2
>> \ 120 = operands 1 and 3 encoded in MODRM-Byte
>> \ 77   = immediate byte (bit 4-7) contains 4th operand
>> \ 00   = immediate byte (bit 0-3) = 0
>>
>>
>> i look forward to comments.
>>
> IMHO, since fpc's x86 assembler is based on NASM, the best way would 
> be to stay as close to NASM format as possible.
>
is not simple.

Nasm: VBLENDVPD    ymmreg,ymmreg*,ymmrm256,ymmreg    [rvms:    
vex.nds.256.66.0f3a.w0 4b /r /is4]    AVX,SANDYBRIDGE
             VADDPS        xmmreg,xmmreg*,xmmrm128                       
[rvm:    vex.nds.128.0f 58 /r]            AVX,SANDYBRIDGE

fpc       VBLENDVPD  xmmreg,xmmreg,xmmrm,xmmreg   
\361\362\372\1\x4B\75\120\77\x00
             VADDPS          Xmmreg,xmmreg,xmmrm                  
\362\370\1\x58\75\120                AVX,SANDYBRIDGE



> Sergei
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>
>

Torsten