[fpc-devel] volatile variables

Michael Schnell mschnell at lumino.de
Thu Jun 30 14:50:13 CEST 2011

On 06/29/2011 09:44 PM, Vinzent Höfler wrote:
> If they are accessed by only one thread, I'd assert that each core's view
> on its own cache is not susceptible to memory ordering issues
I don't suppose this is that simple.

AFAIK, the cache does not work on byte addresses, but on entities of 
cache lines that are 128 byte or whatever.

So a cache can't see if a certain variable is accessed by another 
thread, but needs to store and reload a complete line.

Thus one CPU might modify a value and write back the cache line while 
another CPU modified a value of another variable in the same cache line.

As this situation obviously is handled by the hardware, I do suppose 
that the case of multiple CPUs modifying the same variable is handled, 
too (but of course without software considerations not regarding the 
hardcore cases like an atomic read-modify-write access or cycle-level 
memory ordering).


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