[fpc-devel] volatile variables

[Andrew Brunner]

On Thu, Jun 30, 2011 at 4:31 AM, Hans-Peter Diettrich
<DrDiettrich1 at aol.com> wrote:
>
> After these considerations I'd understand that using Interlocked
> instructions in the code would ensure such read/write-through, but merely as
> a side effect - they also lock the bus for every instruction, what's not
> required when concurrent access has been excluded by other means before.

I too have come to that conclusion.  It remains to be seen/decided
though, who's responsibility is it to ensure/enforce coherency?
Jonas was suggesting that the posix implementation (but he probably
meant kernel) was already doing that via CriticalSection.

> Furthermore we need concrete examples[2], how (to what extent) it's required
> to use these special instructions/procedures, in examples like above. When
> cache synchronization is a big issue, then the usage of related
> (thread-unaware) objects should be discussed as well, i.e. how to ensure
> that their use will cause no trouble, e.g. by invalidating the entire cache
> before.

Some FPC work may have been done in this area - intentional or not.