[fpc-devel] SMP > 2 core Cache issue with Posix threads

[Andrew Brunner]

On Fri, Jul 1, 2011 at 12:48 PM, José Mejuto <joshyfun at gmail.com> wrote:
> This code will crash at a given time, maybe 1 millisecond, maybe 2
> days, but it will crash.

Yes.  It will fail.  Access to a,b are forbidden without acquiring a lock.

> Cache coherence is maintained by the hardware, interlocked only
> provide atomicity. How the atomicity is provided is beyond the scope
> of pascal and even the OS.

IMO, this statement is pretty bold/broad.  Meaning interlocked
assignments as defined will ensure cache coherence as apposed to
CrticialSections which are meant to minimally block *write* access if
not read/write access.

I can tell you that a,b in my case were not so trivial.  a,b happen to
be reference pointers in a collection that without going into too much
detail were certainly paged since the collection they resided in was
large.