[fpc-devel] SMP > 2 core Cache issue with Posix threads

[Andrew Brunner]

On Fri, Jul 1, 2011 at 11:44 AM, Hans-Peter Diettrich
<DrDiettrich1 at aol.com> wrote:

> IMO a linked list can not work flawlessly, until at least a
> multiple-read-exclusive-write lock is used. While an exclusive-write lock
> can ensure list consistency, every unsynchronized reader will be fooled by
> concurrent changes to the list structure :-(

I agree.  Without a memory barrier, coupled with interlocked exchanges
per node attachment, it would make memory synchronization impossible.

> Consider what will happen when an (unsynchronized) reader determined an list
> node, before or after which a new node shall be inserted. When the
> write-synchronized update will happen, the list structure already can have
> changed, so that the referenced node can have changed its position in the
> list, or can have been moved into a very different list :-(

Impossible to comprehend, that's why we have barriers.  But in one
specific case, Interestingly enough - the problem I experienced was
with the 1 owning thread accessing the list. There was no subsequent
access via additional threads, but across cores on a single cpu.