[fpc-devel] SMP > 2 core Cache issue with Posix threads

[Mark Morgan Lloyd]

Michael Schnell wrote:
> In another topic (now closed) Andrew described that a code similar to 
> HansPeter's example did run correctly on a dual core machine, but 
> produced errors on a machine with more cores.

I've not been reading every message. Definitive URL?

> OTOH if some synchronization ensures that the appropriate code sequences 
> that sets it has been executed, IMHO, Posix compatibility of the 
> infrastructure (compiler, libraries, OS, Hardware) ensures that another 
> thread in fact gets that correct value of that variable (i.e. SMP Cache 
> synchronization after the synchronization is granted).

So the really big question is whether any given computer has a robust 
SMP implementation, or if in actual fact it's some species of NUMA with 
unreliable cache coherency.

It might also be necessary to distinguish between SMP, multicore and 
hyperthreading.

> (It it fails only on Andrew's machine, my suggestion is a hardware 
> problem.)
> 
> Who has a >2 Core machine to test and debug this ?

Biggest x86 system I've got here is a Compaq with 2x Xeons which I think 
are 2x multicore rather than HT. More interestingly I've got a 12-way 
SMP Sun, and they've been in this game for a while. Linux-only in both 
cases.

-- 
Mark Morgan Lloyd
markMLl .AT. telemetry.co .DOT. uk

[Opinions above are the author's, not those of his employers or colleagues]