[fpc-devel] threadvar implementation

[Michael Schnell]

  On 08/05/2010 11:19 AM, Hans-Peter Diettrich wrote:
> Michael Schnell schrieb:
>>
>> See http://flint.cs.yale.edu/cs422/doc/24547212.pdf page 3-7
>>
>> The "logical address" is 24 bits: 16 bits "Segment Selector" and 32 
>> bits "Offset".
>
> Please be a bit more precise with your bitcounts.
Sorry for the typo of course the Graphic shows an  48 Bit "Logical 
address" consisting of a 16 bit "Segment Selector" and a 32 bit "Offset" ;)

-Michael