[fpc-devel] ARM-Linux, ARMv5 runtime detection fails

[Florian Klaempfl]

Bernd Mueller schrieb:
> Bernd Mueller wrote:
>>
>> You chose ldrd r0, [sp] to force the SIGILL on ARMv4. According to the
>> docs the load address has to be double word (8 byte) aligned,
>> otherwise a Bus Error/Misaligned data access Error on ARMv5 would
>> occur. Is it save to use sp in your way?
> 
> ok, it does not work. This is what I guessed. But I am in doubt about
> your current fix:
> 
>   asm
>     bic r0,sp,#7
>     ldrd r0,[r0]
>   end;
> 
> r0 is double word (8 byte) aligned now, but does it always point to a
> valid memory location? IMHO something like that would be better:

Yes, this can be safely assumed imo

> 
> procedure fpc_cpucodeinit;
> var
>    qw: QWord;
> begin
> {$ifdef FPC_SYSTEM_FPC_MOVE}
>   cpu_has_edsp:=true;
>   in_edsp_test:=true;
>   asm
>     ldrd r0, qw
>   end;
>   in_edsp_test:=false;
>   if cpu_has_edsp then
>     moveproc:=@move_pld
>   else
>     moveproc:=@move_blended;
> {$endif FPC_SYSTEM_FPC_MOVE}
> end;
> 
> It fails too, because qw is not correct aligned (bug/feature), but this
> is another question ;-)

Does the ARM ABI require that the stack is aligned to 8 byte boundaries?