[fpc-devel] NIOS/2

[Michael Schnell]

Felipe Monteiro de Carvalho wrote:
> What is the architecture of NIOS/2 ? Something standard or it has it's
> own design for opcodes, registers, etc?
>
It's a propriety design of Altera's and seems a little bit similar to ARM.

The NIOS is a very standard RISK processor with load/store architecture 
(like ARM: there are only some dedicated instructions that can access 
the memory)

all arithmetics is done within the registers. <RA=RB+RC>  or can use a 
16 Bit immediate.

The return value of a call is in a dedicated register

It has 32 general purpose registers and no dedicated address registers.
It accesses 2 GB of Memory.
It can be configured is several ways (1, 5 or 6 stage pipeline, with our 
without hardware mult, div, and other instructions

You can d/l the data sheet here:

http://www.altera.com/literature/lit-nio2.jsp

or directly at

http://www.altera.com/literature/hb/nios2/n2cpu_nii5v1.pdf


Look here for the NIOS Linux support:
go to http://www.niosforum.com/
-> Forum
create an account

after that you can d/l a Linux distribution including Eclipse based 
development tools
(that need a working (and fitting version of the) Altera NIOS 
development tools that can be loaded here:

ftp://ftp.altera.com/outgoing/release/quartusii_60_pc.zip
ftp://ftp.altera.com/outgoing/release/megacore_lib_60_pc.zip
ftp://ftp.altera.com/outgoing/release/niosii_60_eval_pc.exe
ftp://ftp.altera.com/outgoing/release/quartusii_60_sp1_pc.exe

The Altera tools can be used in a "Web edition" testing mode for free. 
To create a sell product to be distributed you need an appropriate license.

-Michael

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