[fpc-devel] RISC-V separating Zicsr and Zifencei from base ISA

[Christo Crause]

A while ago the GNU RISC-V toolchain [1] implemented separation of
the Zicsr and Zifencei options from the base integer ISA according to the
ISA spec 20191213.  Espressif bumped their GNU toolchain for esp-idf v5.1
to GCC 12.2 in June 2023, which requires explicitly specifying the Zicsr
and Zifencei extensions to binutils when trying to assemble and link code
using these extensions.  Since binutils 2.36 explicitly passing these
extensions as part of -march is required by default.

How should this be included in the compiler?
a) Change all the subarch names to explicitly include the extensions where
supported, e.g. change rv32_imac to rv32_imac_zicsr_zifencei.
Going forward this is probably the better option since the subarch name
includes all the supported extensions explicitly?
b) Keep the subarch names as current, add the cpu flags to the subarch and
automatically append the extensions to the -march option passed to binutils.

1. https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4
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