[fpc-devel] threadvar implementation

[Michael Schnell]

  On 08/05/2010 11:19 AM, Hans-Peter Diettrich wrote:
>
> Please accept that no more than 3 different segments are in use nowadays. 

This is not true.

1) FS: as discussed in this thread, Windows uses FS to address the 
thread management block
2) ES: in my tests I modified ES in ASM code in a Delphi program and 
caused it to crash by this, So the Delphi compiler seems to use it (for 
whatever purpose)
3a) GS: is used to address threadvars with Linux
3b) in my tests I modified GS in ASM code ion a Delphi program and 
caused it to crash the debugger when single-stepping

User software is free to use ES, FS and GS in a decent way


Anyway, we are talking about the processor hardware here to explore what 
the compiler might be allowed to do and how to do it. Of course the OS 
and compiler internals imposes additional restrictions.
> FS/GS for non-zerobased segments, all others are zero-based.
I have no idea what you mean by "zerobased".

Regarding the processor hardware, address calculations is done with the 
same algorithm, independent of what segment register is used in the 
instruction.

The only different that _as_a_default_ for certain address calculations 
certain segment registers are used. For calculating the address of an 
memory argument in an instruction the normal use (of DS) can be 
overridden by a flag that can be set by a prefix instruction, so that 
instead of DS one of CS, SS, GS or FS is to be used.

The defaults are
  - CS for instruction address
  - DS for memory operator address unless SP-relative
  - SS for memory operator address when SP-relative

-Michael