[fpc-pascal] Memory alignment with FPC

[Marco van de Voort]

In our previous episode, Nico Erfurth said:
> x86 can handle unaligned access, but most implementations (I think
> current atoms and via nano are an exception) will suffer a rather high
> performance penalty.

I thought most modern x86's only had a penalty when an unaligned
access crossed a cacheline boundery ? (32 bytes now, 64 bytes on Haswell)