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<div class="moz-cite-prefix">On 16/02/2022 21:21, Dmitry Boyarintsev
via fpc-devel wrote:<br>
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cite="mid:CAMpTZrfFRv5JemW8poKync6y=2g_h-_PrXtci0DFK6n8e4dhLg@mail.gmail.com">
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<div dir="ltr">On Wed, Feb 16, 2022 at 3:17 PM Martin Frb via
fpc-devel <<a href="mailto:fpc-devel@lists.freepascal.org"
moz-do-not-send="true" class="moz-txt-link-freetext">fpc-devel@lists.freepascal.org</a>>
wrote:<br>
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<blockquote class="gmail_quote" style="margin:0px 0px 0px
0.8ex;border-left:1px solid
rgb(204,204,204);padding-left:1ex">Anything similar on M1?<br>
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<div>should it be ARM64 calling convention?</div>
<div><a
href="https://en.wikipedia.org/wiki/Calling_convention#ARM_(A64)"
moz-do-not-send="true" class="moz-txt-link-freetext">https://en.wikipedia.org/wiki/Calling_convention#ARM_(A64)</a>
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Possible. I have a bit of disassembly, a callstack, and a listing of
register values at that call. They suggest its x0 x1 and x2<br>
<br>
I just hoped for some definite confirmation by someone who knows for
sure.<br>
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