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I don't have an M1 myself, but according to the data from the thread
on the lazarus mail list, there is a bug in the 3.3.1 asm generator
for M1<br>
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var pn8: pint8; // pointer signed byte<br>
<br>
In the below expression ...(not pn8^)...<br>
<br>
"pn8^" is loaded to w0 and sign extended. From this point onwards
operations on the value should be 32 bits (the value has been
extended, and the full 32 bits are later used).<br>
but "not" only affects the lowest 8 bit.<br>
<br>
Apparently in 3.2.2 (or was it 3.2.0) there was<br>
mvn w0,w0<br>
<br>
If someone can confirm tihs....<br>
<br>
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<td>[Lazarus] fpc bug with M1 [[was: Re: UTF8LengthFast
returning incorrect results on AARCH64 (MacOS)]]</td>
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<th valign="BASELINE" nowrap="nowrap" align="RIGHT">Date: </th>
<td>Tue, 28 Dec 2021 22:47:53 +0100</td>
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<th valign="BASELINE" nowrap="nowrap" align="RIGHT">From: </th>
<td>Martin Frb via lazarus
<a class="moz-txt-link-rfc2396E" href="mailto:lazarus@lists.lazarus-ide.org"><lazarus@lists.lazarus-ide.org></a></td>
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<td>Lazarus mailing list
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<td><a class="moz-txt-link-abbreviated" href="mailto:lazarus@lists.lazarus-ide.org">lazarus@lists.lazarus-ide.org</a></td>
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<td>Martin Frb <a class="moz-txt-link-rfc2396E" href="mailto:lazarus@mfriebe.de"><lazarus@mfriebe.de></a></td>
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<br>
<br>
<br>
# [43] Result += (pn8^ shr 7) and ((not pn8^) shr 6);<br>
ldr x0,[sp]<br>
ldrsb w0,[x0] # <<<<< sign extend to
a 32bit value (32bit register).<br>
eor w0,w0,#255 # <<<<< But only "not" the
lowest 8 bit. That is wrong. The calculation uses 32 bit at this
point<br>
lsr w0,w0,#6<br>
ldr x2,[sp]<br>
ldrsb w2,[x2]<br>
lsr w2,w2,#7<br>
and w0,w2,w0 # <<<<<< here the full 32
bit are used.<br>
<br>
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