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    <p>If needs be, I can easily build on this merge request later to
      fill the saved register arrays if a particular architecture has a
      tailor-made solution.</p>
    <p>Note that the volatile registers are not saved in this array and
      are checked separately. (e.g. in aoptx86.pas, the method
      GetIntRegisterBetween, which could theoretically be made
      platform-independent (it contains some conditional code for i386
      because 8-bit registers can only be AL, CL, DL and BL), calls "<span
        id="LC1072" class="line" lang="">RegSet :=</span><span
        id="LC1073" class="line" lang="">
paramanager.get_volatile_registers_int(current_procinfo.procdef.proccalloption)
        +</span><span id="LC1074" class="line" lang="">
        current_procinfo.saved_regs_int;" to get the list of registers
        available to the current procedure.  While this is slightly
        slower, I figure it's a bit more flexible and
        backward-compatible.</span></p>
    <p><span id="LC1074" class="line" lang="">Gareth aka. Kit<br>
      </span>
    </p>
    <div class="moz-cite-prefix">On 27/12/2021 19:32, J. Gareth Moreton
      via fpc-devel wrote:<br>
    </div>
    <blockquote type="cite"
      cite="mid:fe31846f-5e3d-979c-068c-d83e8d2e5e19@moreton-family.com">Hi
      Florian et al,
      <br>
      <br>
      I fixed up the CPU subtype in
      <a class="moz-txt-link-freetext" href="https://gitlab.com/freepascal.org/fpc/source/-/merge_requests/104">https://gitlab.com/freepascal.org/fpc/source/-/merge_requests/104</a>
      - hopefully the merge request is good now.
      <br>
      <br>
      Gareth aka. Kit
      <br>
      <br>
      <br>
    </blockquote>
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