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<p>Perhaps someone can help me with interrupts on riscv32:</p>
<p>I have now changed the compiler to create proper interrupt
routines, all used registers are saved on stack, so far so good:</p>
<p><tt>MTIP_ISR:</tt><tt><br>
</tt><tt>.Lc2:</tt><tt><br>
</tt><tt> sw x1,-4(x2)</tt><tt><br>
</tt><tt> sw x8,-8(x2)</tt><tt><br>
</tt><tt> sw x10,-12(x2)</tt><tt><br>
</tt><tt> sw x11,-16(x2)</tt><tt><br>
</tt><tt> addi x8,x2,0</tt><tt><br>
</tt><tt> <b>addi x2,x2,-68</b></tt><tt><br>
</tt><tt>.La1:</tt><tt><br>
</tt><tt> auipc x10,%pcrel_hi(U_$P$TEST_$$_SYSTICKCOUNTER)</tt><tt><br>
</tt><tt> addi x10,x10,%pcrel_lo(.La1)</tt><tt><br>
</tt><tt> lw x11,0(x10)</tt><tt><br>
</tt><tt> addi x11,x11,1</tt><tt><br>
</tt><tt> sw x11,0(x10)</tt><tt><br>
</tt><tt> <b>addi x2,x8,0</b></tt><tt><br>
</tt><tt> lw x11,-16(x2)</tt><tt><br>
</tt><tt> lw x10,-12(x2)</tt></p>
<p><tt> lw x8,-8(x2)</tt><tt><br>
</tt><tt> lw x1,-4(x2)</tt><tt><br>
</tt><tt> mret</tt><br>
</p>
<p>but I am a little uncertain with stackframe size.</p>
<p>For mipsel I did tweak function
trv32procinfo.calc_stackframe_size:longint in cpupi.pas to
increase the stackframe size so that the stackframe can hold all
registers in worst case, when using interrupts also temp registers
must be saved on stack when they are used.<br>
</p>
<p>but in risc32 this function looks a lot different, I cannot see
any handling of int registers, only float seems to be covered.</p>
<p>calc_stackframe size is used to calc localsize in g_proc_exit, to
better understand if I have covered all cases, how can I make
localsize var > 0? <br>
</p>
<p>From the generated code I see that in my example code localsize
must have been <=0. I tried adding local vars to the interrupt
routine but this did not change the generated code, only
stackframe size was adjusted as expected so localsize must still
have been <=0<br>
</p>
Can you please point me in the right direction?
<p>Thank you,</p>
<p>Michael</p>
<p>Interrupt Routine with two local vars:<br>
</p>
<p><tt>MTIP_ISR:<br>
.Lc2:<br>
sw x1,-4(x2)<br>
sw x8,-8(x2)<br>
sw x10,-12(x2)<br>
sw x11,-16(x2)<br>
addi x8,x2,0<br>
<b>addi x2,x2,-76</b><br>
.La1:<br>
auipc x10,%pcrel_hi(U_$P$TEST_$$_SYSTICKCOUNTER)<br>
addi x10,x10,%pcrel_lo(.La1)<br>
lw x11,0(x10)<br>
addi x11,x11,1<br>
sw x11,0(x10)<br>
lw x10,-56(x8)<br>
addi x10,x10,1<br>
sw x10,-56(x8)<br>
lw x10,-56(x8)<br>
sw x10,-60(x8)<br>
<b>addi x2,x8,0</b><br>
lw x11,-16(x2)<br>
lw x10,-12(x2)<br>
lw x8,-8(x2)<br>
lw x1,-4(x2)<br>
mret</tt><tt></tt><br>
</p>
<p>Pascal Version:</p>
<p><tt>procedure SysTick_interrupt; [interrupt, public, alias:
'MTIP_ISR'];</tt><tt><br>
</tt><tt>var</tt><tt><br>
</tt><tt> x : integer;</tt><tt><br>
</tt><tt> y : integer;</tt><tt><br>
</tt><tt>begin</tt><tt><br>
</tt><tt> Inc(SysTickCounter);</tt><tt><br>
</tt><tt> x := x+1;</tt><tt><br>
</tt><tt> y := x;</tt><tt><br>
</tt><tt>end;</tt><br>
</p>
<div class="moz-cite-prefix">Am 12.01.20 um 01:04 schrieb Michael
Ring:<br>
</div>
<blockquote type="cite"
cite="mid:77623321-577a-e02d-99ad-4d8e6d1b296e@michael-ring.org">
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<p>Here's my latest patch, I have included an (untested) unit for
gd32vf103 chips....</p>
<p>The defines for interrupts should be correct, but I did not
start testing if interrupts work. for the sifive chips the
interrupts are definitively wrong, but this will be my next step
to fix as I work more in the sifive board.</p>
<p>Have fun,</p>
<p>Michael<br>
</p>
<div class="moz-cite-prefix">Am 04.01.20 um 13:50 schrieb Michael
Ring:<br>
</div>
<blockquote type="cite"
cite="mid:834041fb-1729-9fa2-60da-1298997dcc85@michael-ring.org">
<meta http-equiv="Content-Type" content="text/html;
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<p>The Boards are on their way, I found a second Sipeed MAIX
board with a Kendryte K210 chip, this should cover the 64bit
World. Shipping should take 3-5 days.</p>
<p>I will see that I can come up with a prelimary unit-file for
the K210</p>
<p>Have fun with the boards,</p>
<p>Michael<br>
</p>
<div class="moz-cite-prefix">Am 03.01.20 um 20:13 schrieb Jeppe
Johansen:<br>
</div>
<blockquote type="cite"
cite="mid:742521e3-352a-dbd7-7ac4-fb99c152370a@j-software.dk">
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<p>Nice, thanks :)<br>
<br>
Jeppe Johansen<br>
Alexander Foss Gade 12, 3, 6<br>
9000 Aalborg<br>
Denmark<br>
<br>
Hmm okay. Never seen a crash, but I haven't been using the
32bit toolchain that much<br>
Currently I use 2.32.51.20190629. Built from upstream
d6954c38df90637bc1b0cc2b20473e2754e5eff7<br>
<br>
Best Regards,<br>
Jeppe<br>
</p>
<div class="moz-cite-prefix">On 1/3/20 7:41 PM, Michael Ring
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:2558e262-28f5-e724-9797-8aab144e5eda@michael-ring.org">
<meta http-equiv="Content-Type" content="text/html;
charset=UTF-8">
<p>I will be more than happy to provide a board to you....
Please send me you smail address, will send you a board.</p>
<p>compiling now works fine with debuginfo but the linker
crashes. Most likely a problem in my linker script, just
to be sure, which binutils do you use?</p>
<p>Michael<br>
</p>
<div class="moz-cite-prefix">Am 03.01.20 um 18:10 schrieb
Jeppe Johansen:<br>
</div>
<blockquote type="cite"
cite="mid:8d18b844-91b4-deca-1a49-c0a841a03daa@j-software.dk">
<meta http-equiv="Content-Type" content="text/html;
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<p>Hi Michael,<br>
<br>
I just fixed that. There was a very specific workaround
in the fpc dwarf writer but only riscv*-linux was added,
not embedded.<br>
<br>
I would be glad to buy a Longan Nano off you. Thought
about getting those before but never got around to
ordering some.<br>
<br>
Best Regards,<br>
Jeppe<br>
</p>
<div class="moz-cite-prefix">On 1/3/20 1:31 PM, Michael
Ring wrote:<br>
</div>
<blockquote type="cite"
cite="mid:648150d1-ef94-06da-3f94-6cf8a20d2661@michael-ring.org">
<meta http-equiv="Content-Type" content="text/html;
charset=UTF-8">
<p>Things are slowly progressing for me, there is one
thing that bugs me, I cannot use Debug Info because I
then get:</p>
<p>Error: non-constant .uleb128 is not supported</p>
<p>I found a few articles online on the issue and tried
to replace my default riscv32-embedded-as (built from
latest gnu binutils) with a version built out of the
original risc-v git but this did not change a thing.</p>
<p>Did you also encounter this? Which binutils package
do you use?</p>
<p>If you are interested then I can send you a logan
nano, I bought three of them....<br>
</p>
<p>Happy new year,</p>
<p>Michael<br>
</p>
<div class="moz-cite-prefix">Am 16.12.19 um 13:05
schrieb <a class="moz-txt-link-abbreviated"
href="mailto:jeppe@j-software.dk"
moz-do-not-send="true">jeppe@j-software.dk</a>:<br>
</div>
<blockquote type="cite"
cite="mid:6y81z9-r3rzbbf1i8jfoszr1vavt4vbtfkqgf-kkmu7fd6d99m2gnrsv-w82cxf-fjsqfg3pugg8k429gz-kkm66x-oegia9-osypdo-sgvd1b-9k0kw1hw0a8fd3y8u-ve73wl16mw3j58ht3mu5ngu.1576497930353@email.android.com">
<meta http-equiv="content-type" content="text/html;
charset=UTF-8">
<div dir="auto">Hi Michael
<div><br>
</div>
<div>Looks like a good start. I have yet to get my
hands on some actual boards but I'll probably get
some sipeeed ones soon</div>
<div><br>
</div>
<div>For the startup code the only tricky part is
the initialization of the GP register. The
rest(init of .data and .bss) can be done as Pascal
code. </div>
<div>You can see how that's done in the Linux 64
startup code </div>
<div><br>
</div>
<div>We should probably add an intrinsic to
read/write to the csrs in case that's needed. Also
for the other system instructions </div>
<div><br>
</div>
<div>Best regards, </div>
<div>Jeppe<br>
<br>
</div>
</div>
<div style="line-height:1.5"><br>
<br>
-------- Original message --------<br>
From: Michael Ring <a class="moz-txt-link-rfc2396E"
href="mailto:mail@michael-ring.org"
moz-do-not-send="true"><mail@michael-ring.org></a><br>
Date: Sun, 15 Dec 2019, 20:57<br>
To: <a class="moz-txt-link-abbreviated"
href="mailto:jeppe@j-software.dk"
moz-do-not-send="true">jeppe@j-software.dk</a><br>
Subject: Getting my feet wet with risc-v<br>
<blockquote>
<div>
<p>Hi Jeppe,</p>
<p>hope all is fine with you!</p>
<p><br>
</p>
<p>I finally started to play arround with risc-v
target, so far I have added two boards (Units
for boards are not final, only a first try). I
have a GD32VF103CBT6 based board (Sipeed
Longan Nano) and a sifive FE310-G002 based
board (HiFive1RevB) and now started with the
HiFive Board as it has a Segger JLink on-Board
which will make debugging a lot easier.<br>
</p>
<p>What I wanted to ask you, did you already
create startup code for riscv32/riscv64? <br>
</p>
<p>I am not yet very fluent in risc-v assembler
so I wanted to steal some code from you in
case you have something.</p>
<p>Nevermind if you do not have something, it
should be pretty straightforward to port the
arm startup code to risc-v</p>
<p>I still need to do the linker script in
systems/t_embed.pp, so do not expect too much
from my patch ;-)</p>
<p><br>
</p>
<p>Michael<br>
</p>
</div>
</blockquote>
</div>
</blockquote>
</blockquote>
</blockquote>
</blockquote>
</blockquote>
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