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<p class="MsoNormal">Hello,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I have been working on some embedded (no OS) development on ARMv6 and ARMv7 (Raspberry Pi and Raspberry Pi 2) using FPC 3.1.1 trunk.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Because these devices have a fairly large amount of memory I have been using ARM instruction set (-CIARM option) to simplify the assembler code required for the low level interfaces, however early on I noticed that if I specify the options
-CpARMV7A (or -CpARMV6) and –CIARM I end up with code that doesn’t work.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I traced the problem to the use of BLX <Label> instructions which according to the ARM documentation seem to always causes an unconditional change to Thumb state. If I remove the CPUARM_HAS_BLX_LABEL capability and rebuild the compiler
the code produced uses only BL <Label> and always works correctly. There seems to be no problem with BLX <Register> or BX <Register> instructions which use bit[0] of the register to determine the target state.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">There appear to be only two places in the compiler and RTL code where CPUARM_HAS_BLX_LABEL and ARM state needs to be handled, these are:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">\source\compiler\arm\cgcpu.pas<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Which in tbasecgarm.a_call_name has something like<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"> if (CPUARM_HAS_BLX_LABEL in cpu_capabilities[current_settings.cputype]) and<o:p></o:p></p>
<p class="MsoNormal"> { WinCE GNU AS (not sure if this applies in general) does not support BLX imm }<o:p></o:p></p>
<p class="MsoNormal"> (target_info.system<>system_arm_wince) then<o:p></o:p></p>
<p class="MsoNormal"> branchopcode:=A_BLX<o:p></o:p></p>
<p class="MsoNormal"> else<o:p></o:p></p>
<p class="MsoNormal"> branchopcode:=A_BL;<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This could easily be changed to<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"> if (CPUARM_HAS_BLX_LABEL in cpu_capabilities[current_settings.cputype]) and<o:p></o:p></p>
<p class="MsoNormal"> { WinCE GNU AS (not sure if this applies in general) does not support BLX imm }<o:p></o:p></p>
<p class="MsoNormal"> (target_info.system<>system_arm_wince) and<o:p></o:p></p>
<p class="MsoNormal"> (current_settings.instructionset <> is_arm) then<o:p></o:p></p>
<p class="MsoNormal"> branchopcode:=A_BLX<o:p></o:p></p>
<p class="MsoNormal"> else<o:p></o:p></p>
<p class="MsoNormal"> branchopcode:=A_BL;<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">to account for the ARM state.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The other occurrence is in the assembler code in \source\rtl\arm\arm.inc for fpc_ansistr_decr_ref which has<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal" style="text-indent:36.0pt">{$if defined(CPUARM_HAS_BX) and not(defined(WINCE))}<o:p></o:p></p>
<p class="MsoNormal" style="text-indent:36.0pt"> blx InterLockedDecrement<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This should probably be changed to defined(CPUARM_HAS_BLX_LABEL) instead but that doesn’t deal with the selected instruction set (ARM or Thumb). Obviously the CPU capabilities are available as defines at this point but I cannot actually
find anywhere that the IS_ARM / IS_THUMB settings also end up as defines.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Before I go ahead and log this as a bug report is there anyone who can comment on whether :<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoListParagraph" style="text-indent:-18.0pt;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="mso-list:Ignore">a)<span style="font:7.0pt "Times New Roman"">
</span></span><![endif]>There is something I am misunderstanding in the ARM documentation about BLX <Label> and the switch to Thumb state?<o:p></o:p></p>
<p class="MsoListParagraph" style="text-indent:-18.0pt;mso-list:l0 level1 lfo2"><![if !supportLists]><span style="mso-list:Ignore">b)<span style="font:7.0pt "Times New Roman"">
</span></span><![endif]>How the use of BLX <Label> in \rtl\arm\arm.inc might be resolved (is there actually a define that reflects ARM or Thumb state selection)?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">One more thing, just wanted to give a big congratulations to the FPC dev team. I have been working on this project for several months and have a fully working embedded core including pre-emptive threading, lock primitives, multicore support,
memory management, hardware exceptions, interrupt handling, DMA, USB, filesystem, network etc which is 100% Free Pascal and this is the only issue I have encountered that I could directly trace to FPC itself. Thanks to you all for such a powerful compiler!<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Garry Wood.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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