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It's big endian on big endian architectures.<br><br>Which arhictecture(s) does big endian?<br><br><div class="gmail_quote">On Fri, Jul 31, 2009 at 11:29 AM, Jonas Maebe <span dir="ltr"><<a href="mailto:jonas.maebe@elis.ugent.be">jonas.maebe@elis.ugent.be</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"><div class="im"><br>
On 31 Jul 2009, at 13:21, Desmond Coertzen wrote:<br>
<br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
As far as endian is concerned: Integer types i found always to be little<br>
endian in most pascal compilers by default.<br>
</blockquote>
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It's big endian on big endian architectures.<div class="im"><br>
<br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
As far as the FPC compiler is concerned, this should not be a concern as it<br>
seems the decisions regarding the byte order was made and cemented in place<br>
long ago. But now that you guys mention byte order, are there directives in<br>
FPC where integer byte orders can be changed?<br>
</blockquote>
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No, it's always the native byte order of the underlying architecture.<div class="im"><br>
<br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
If language syntax might be extended to provide bit width accessibility for<br>
MCU's, i think the same methods must be followed throughout FPC: In all<br>
technical specifications I have come accross, bit 0 is always the least<br>
significant bit of any word regardless the size of the word. That makes<br>
things simple.<br>
</blockquote>
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At least in the PowerPC documentation (both from Motorola and IBM), bit 0 is always the most significant bit.<br><font color="#888888">
<br>
<br>
Jonas</font><div><div></div><div class="h5"><br>
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